- Example designs using HBM BCAM do not run using the XSIM or Xcelium Simulators (refer to AXI High Bandwidth Controller LogiCORE IP Product Guide (PG276), Chapter 6.)
- Netlist (post-synthesis and post-implementation) simulations are not supported with any HBM-based design (refer to AXI High Bandwidth Controller LogiCORE IP Product Guide (PG276), Chapter 1.)
- CAMs implemented in BRAMs can sometimes experience timing failures on the BRAM Cascade paths (of depth 4) when running at high frequencies in -2LV AMD UltraScale+™ devices. If this occurs, it is recommended to force these CAMs to URAM to avoid this problem.
- There is an issue in the TinyBCAM/TinyTCAM software driver code reset functions (within the TinyCamCommonReset function) where it can cause errors in the TinyBCAM/TinyTCAM programming if it is called when the table is completely full (all entries occupied). A workaround is to delete each table entry individually instead of using the reset function.