Using the Vitis Environment in the Design Flows - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-10
Version
2023.1 English

The Vitis environment comprises tools, libraries, and IP that let you program, run, and debug the different elements of a Versal adaptive SoC application, including AI Engine kernels and graphs, programmable logic (PL) functions, and software applications running on the processing system (PS). The Vitis tools use a platform-based approach in which the system is conceptually divided into the following elements, which can be developed and tested in parallel:

  • Platform
  • Adaptable subsystem
  • Software application

The following figure shows the elements used in this platform-based approach.

Figure 1. Custom Platform, Adaptable Subsystem, and Software Application

Platforms

Platforms provide the foundational hardware IP blocks and software features upon which the adaptable subsystem and software application can be built and integrated. Platforms comprise two parts: the hardware platform and the software platform. The hardware platform contains the foundational Versal hardware IP blocks, including CIPS, NoC, I/O controllers, AI Engine array, and other user-specified IP blocks. The software platform defines the domains, device tree, and OS.

The platform insulates application developers from the details of the low-level infrastructure, allowing them to focus on development of a specific function of the adaptable system, such as the software, AI Engine graph, or PL kernel logic. The hardware side of the platforms is created using the Vivado tools. The software side of the platforms is created using PetaLinux or Yocto.

Adaptable Subsystems

Adaptable subsystems perform well-defined functions, leveraging PL blocks and AI Engine graphs (for devices that include AI Engines). The PL blocks in adaptable subsystems are commonly referred to as PL kernels. PL kernels can be RTL, Vivado IP, or high-level synthesis (HLS) blocks. The AI Engine program is developed using a dataflow graph specification written in C++. The different components of an adaptable system are individually designed and verified before being assembled and integrated with a platform using the Vitis linker.

Software Application

The software application runs on the PS and performs high-level application tasks while interacting with the adaptable subsystem. The software application is developed using the Vitis embedded software development flow.

Vitis Tools

The following Vitis tools facilitate the creation, verification, and integration of the different elements of the complete system:

AI Engine tools
Program, simulate, and debug AI Engine programs. This suite of tools include the aiecompiler, AI Engine simulator (aiesimulator), and x86 simulator (x86simulator).
Vitis HLS and Vitis compiler (v++ --compile)
Creates PL kernels from C/C++ source code.
Vivado IP packager
Packages existing IP or RTL code into Vitis PL kernels.
Vitis linker (v++ --link)
Integrates AI Engine graphs and PL kernels with a platform.
Vitis packager (v++ --package)
Integrates the PS components of the system (the software application) and generates the boot image.
Vitis emulation flow
Simulates the behavior of the PS, PL, and AI Engine components after integration with the Vitis linker and prior to running on actual hardware.
Vitis analyzer
Provides reports generated during compilation, link, and execution of the system created using the Vitis tools.
Vitis embedded software development flow (with the system software stack including PetaLinux)
Provides support for the PS domain of the embedded processor.
Note: Model Composer is also available for users familiar with MATLABĀ® software. For more information, see the Vitis Model Composer User Guide (UG1483) and the Vitis Model Composer Examples and Tutorials.

For more information about these tools, see the Vitis Unified Software Platform Documentation (UG1416).