NoC - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

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2023.1 English

The network on chip (NoC) is a high-speed communication subsystem that transfers data between intellectual property (IP) Endpoints in the PL, PS, and other integrated blocks, providing unified intra-die connectivity. The NoC master and slave interfaces can be configured as AXI3, AXI4, or AXI4-Stream. The NoC converts these AXI interfaces to a 128-bit wide NoC packet protocol that moves data horizontally and vertically across the device via the horizontal NoC (HNoC) and vertical NoC (VNoC) respectively. The HNoC runs at the bottom and top of the Versal adaptive SoC, close to the I/O banks and integrated blocks (e.g., processors, memory controllers, PCIe). The number of VNoCs (up to 8 VNoCs) depends on the device and the amount of DDRMCs (up to 4 DDRMCs). For Versal devices that use stacked silicon interconnect (SSI) technology, the NoC connects between the super logic regions (SLRs) using the NoC inter-die bridge (NIDB). For more information on the AXI protocol, see the Vivado Design Suite: AXI Reference Guide (UG1037).

The NoC must be configured or programmed from the NoC programming interface (NPI) at early boot and before the NoC data paths are used. The NPI programs NoC registers that define the routing table, rate modulation, and QoS configuration. Programming of the NoC from the NPI normally requires no user intervention. Programming is fully automated and executed by the platform management controller (PMC)-embedded NPI controller. For more information about boot and configuration, see the Versal Adaptive SoC Technical Reference Manual (AM011).

The Versal adaptive SoC NoC IP acts as the logical representation of the Versal adaptive SoC NoC. The main function of the NoC is to efficiently move data between the DDR controllers and the rest of the device. The Versal adaptive SoC NoC IP enables multiple masters to access a shared DDRMC with advanced quality of service (QoS) settings. The AXI NoC IP is required to connect the PS or the PL to the DDRMC. The AXI NoC IP can also be used to create additional connections between the PS and the PL or between design modules located in the PL.

For more information on the NoC IP and performance, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).