Ethernet MAC - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-10
Version
2023.1 English

If you are migrating from UltraScale or UltraScale+ device Integrated 100G Ethernet (CMAC) hard block or soft 10G/25G/40G or 50G Ethernet IP, consider the following:

  • MRMAC provides wider customization for line rate, clocking, and user interface:
    • Supported configurations are: 1 x 100GE, 2 x 50GE, 1 x 40GE; 4 x 25GE, and 4 x 10GE.
    • MRMAC now has an integrated AXIS interface for MAC+PCS operation as opposed to CMAC, which offered integrated 512-bit LBUS interface with optional AXIS interface.
    • Various AXIS bus widths and clocking options are available and depending on configuration, vary from those available in UltraScale or UltraScale+ device CMAC or soft core solutions.
    • There is a new Flex Port option for access to PCS level.
  • The GT is not included as part of the MRMAC core. IP integrator block automation is used to connect between the MRMAC and GT.
  • Instead of provided statistic counter increment vectors, statistics registers are now integrated as part of the hard block and available over AXI4-Lite.
  • The MRMAC also supports a new high-precision timestamping feature to enable sub-nanosecond accuracy on IEEE Std 1588 timestamps.

For more information on the MRMAC and details on generating the MRMAC example design, see the Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314).