DSP Primitives - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-10
Version
2023.1 English

Following are the different types of DSP primitives for Versal adaptive SoC.

Primitive Description Usage
DSP58 Standard integer/Fixed point mode Inference or instantiation
DSPFP32 Floating point mode Instantiation only
DSPCPLX Complex multiplier Inference or instantiation

DSP58

For Versal adaptive SoCs, the DSP58 primitive includes the same features as in UltraScale devices, including a multiplier, adder, pre-adder, and registers to fully pipeline the primitive. However, sizing differs and the primitives include additional features.

Sizing

For signed logic, you can configure DSP58 as follows:

  • Multiplier: 27x24
  • Adder: 58-bit
  • Pre-adder: 27-bit

For unsigned logic, you can configure DSP58 as follows:

  • Multiplier: 26x23
  • Adder: 57-bit
  • Pre-adder: 26-bit

The following figures show examples for signed logic.

Figure 1. Elaborated View of 27x24 Multiplier with 58-Bit Adder and 27-Bit Pre-Adder
Figure 2. Verilog RTL for a 27x24 Multiplier with 58-Bit Adder and 27-Bit Pre-Adder
Figure 3. VHDL RTL for a 27x24 Multiplier with 58-Bit Adder and 27-Bit Pre-Adder

Dot Product

The DSP58 can implement a dot product, which is a multiplier that is represented as three smaller multipliers that are added together. Dot products are often used in filters in image processing. For more information, see the Versal Adaptive SoC DSP Engine Architecture Manual (AM004). The following figure shows an example of a dot product with an extra adder.

Note: For the dot product to infer, the RTL must use signed logic.
Figure 4. Elaborated View of a Dot Product with an Extra Adder

The following figures show the RTL for a dot product.

Figure 5. Verilog RTL for the Dot Product
Figure 6. VHDL RTL for the Dot Product

DSPFP32

DSPFP32 can perform floating point calculations. Vivado synthesis does not handle these calculations. Instead, various IP are provided, or the DSPFP32 primitive can be instantiated.

DSPCPLX

The DSPCPLX is designed to synthesize logic needed to solve for the real and imaginary portions of the following equation:

(a+bi)(c+di)

Each DSPCPLX occupies two DSP58 sites. The DSPCPLX can either be instantiated in the RTL or inferred. The following figures show the RTL for the DSPCPLX.

Figure 7. Verilog RTL to Synthesize the DSPCPLX
Figure 8. VHDL RTL to Synthesize the DSPCPLX