If you are migrating from AMD UltraScale+™ device families, consider the following:
- UltraScale+ device designs (without PS)
- These devices contain integrated configuration logic that supports a set of configuration modes on power-up. With Versal adaptive SoC, there are changes to the boot and configuration flows, which require the use of the CIPS IP.
- Zynq UltraScale+ MPSoC and Zynq UltraScale+ RFSoC designs (with PS)
- These devices have a PMU and CSU to manage and carry out the boot-up process. With Versal adaptive SoC, there are changes in the boot flow methodology, which rely on the RCU and PPU in the PMC to manage and carry out the boot-up process. In addition, CIPS IP is required to configure the boot peripheral.
For more information on the Versal adaptive SoC boot modes, boot sequence, and boot image, see the following resources:
- This link in the Versal Adaptive SoC Technical Reference Manual (AM011)
- This link in the Versal Adaptive SoC System Software Developers Guide (UG1304)
- Bootgen User Guide (UG1283)
The following table compares the primary boot and configuration modes of UltraScale+ devices with Versal adaptive SoC.
| Mode | Virtex UltraScale+ or Kintex UltraScale+ FPGA | Zynq UltraScale+ MPSoC or Zynq UltraScale+ RFSoC | Versal Adaptive SoC |
|---|---|---|---|
| JTAG | Yes | Yes | Yes |
| OSPI | – | – | Yes |
| QSPI32 |
Yes |
Yes |
Yes |
| QSPI24 |
Yes |
Yes |
Yes |
| SelectMAP | Yes | – | Yes 1 |
| eMMC1 (4.51) | – | Yes | Yes |
| SD1 (3.0) | – | Yes | Yes |
| SD1 (2.0) | – | Yes | Yes |
| SD0 (3.0) | – | – | Yes |
| SD0 (2.0) | – | Yes | – |
| PJTAG_0 | – | – | – |
| PJTAG_1 | – | Yes | – |
| Serial | Yes | – | – |
| BPI | Yes | – | Note 2 |
| NAND | – | Yes | Note 2 |
| USB (2.0) | – | Yes | – |
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