AMBA Specification Interfaces - 2023.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2023-05-10
Version
2023.1 English

The PS-PL Arm Advanced Microcontroller Bus Architecture (AMBA) specification interfaces in the Versal adaptive SoC have similar functionality to Zynq UltraScale+ MPSoCs, as shown in the following table.

Note: Enabling and disabling the different power domains in the LPD, FPD, and PL enables and disables the AXI connections to those domains.
Important: Because the DDRMC is shared between the PS and PL via the device-wide, high-performance NoC interface, there are fewer PS-PL AXI interconnects.
Table 1. AMBA Interface Comparison
PS-PL AMBA Interface Master Coherency Zynq UltraScale+ MPSoC Versal Adaptive SoC
Name Count Name Count
Accelerator Coherency Port (ACP) PL I/O S_AXI_ACP_FPD 1 S_ACP_FPD 1
AXI Coherency Extensions (ACE) PL 2-way S_AXI_ACE_FPD 1 S_ACE_FPD 1
PL-to-FPD AXI PL - S_AXI_HPx_FPD 4 S_AXI_HP 1
PL-to-FPD AXI PL I/O S_AXI_HPCx_FPD 2 S_AXI_HPC 1
PL-to-LPD AXI PL - S_AXI_LPD 1 S_AXI_LPD 1
FPD-to-PL AXI FPD - M_AXI_HPMx_FPD 2 M_AXI_FPD 1
LPD-to-PL AXI LPD - M_AXI_HPM0_LPD 1 M_AXI_LPD 1