DDR Self-refresh over Warm Restart - 2023.1 English

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID
UG1137
Release Date
2023-08-04
Version
2023.1 English

In most systems, the RAM of a computing system is cleared when the system resets or powers down. Any data that needs to be retained, such as settings and logs, are usually stored in a non-volatile memory such as flash and battery backed-up RAM. These non-volatile memories are slower, especially when the amount of data is huge. For some systems, a more preferred solution is to retain the data in the DRAM, thus effectively using it as a non-volatile memory.

The Zynq UltraScale+ MPSoC software solution supports a feature to put DDR into self-refresh mode during warm restart (system reset, or PS only reset). This makes the DDR a non-volatile memory and its contents remain as it is even after a reset.

By default, this feature is disabled. You can enable this feature by enabling the following build flags during PMUFW and FSBL compilation:

PMUFW
ENABLE_DDR_SR_WR
FSBL
XFSBL_ENABLE_DDR_SR

After these build flags are enabled, the PMUFW puts the DDR in self-refresh mode during a warm restart (PS only or System restart).