Xilinx Low Latency Limitations - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

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2023.1 English

The Xilinx low-latency mode has the following limitation:

  • The VCU encoder and decoder use mono-threaded micro-controller based scheduler for sending commands to underlying hardware IP blocks. For the multi-stream environment it is possible that command requests for one stream can get blocked if the scheduler is busy serving commands for another stream in parallel. This may cause momentary spike in latency. Also the spike in latency can occur in an already running pipeline whenever a new pipeline is launched or closed as the command requests for running stream can get blocked while a new channel is being created for encoding a new stream, or an existing channel for an already running stream gets destroyed during closure. Latencies may go higher as the number of streams increase.