Address Offset | Width | Type | Reset Value | Description |
---|---|---|---|---|
0x41064 | 32 | RO | 0x0 | This register describes and reports the fractional value of PLL clock |
Field Name | Bits | Type | Reset Value | Definition |
---|---|---|---|---|
VCU_PLL_CLK_LO | [31:0] | RO | 0x0 |
Reports the fractional value of PLL clock frequency as set in the Vivado block design. Each unit is 10 kHz. Default: 33.33MHz |