The following table shows the latency for the VCU pipeline stages.
Use Case 5 | Capture | Encode (HEVC / AVC) | Decode | Display |
---|---|---|---|---|
Normal Latency | 16.6 ms | 18 ms / 35 ms | 200 ms | 16.6 ms |
Reduced Latency | 16.6 ms | 18 ms / 35 ms | 50 ms | 16.6 ms |
Low Latency | 16.6 ms | 4 ms / 10 ms | 17 ms | 16.6 ms |
Xilinx Low-Latency 3, 4 | 1 ms | 4 ms / 10 ms | 9 ms | 16.6 ms |
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Latency Numbers
Latency numbers are derived from the following equations:
Use Case | Equation 1 | Latency |
---|---|---|
v4l2src | 1 frame period for the capture buffer | 16.66 ms |
omxh265enc (HEVC encoder) | 1 frame period for input capture buffer rounded to ms + 1 ms margin = 17 ms + 1 ms | 18 ms |
omxh264enc (AVC encoder) | 1 frame period for input capture buffer rounded to ms + 1 intermediate buffer + 1 ms margin = 17 ms + 17 ms + 1 ms | 35 ms |
Normal Latency [omxh265dec & omxh264dec (AVC/HEVC Decoder)] | DPB size (5 for default level i.e. 5.2) + internal entropy buffers (default=5) + reconstruction buffers (default=1)+ concealment buffers (default=1) = 12 *16.66 ms | 200 ms |
Reduced Latency | 1 frame period to insert frame into decoder + 1 frame period to decode + 1 frame period margin = 16.6 ms + 16.6 ms + 16.6 ms | 50 ms |
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