The VCU TRD 2023.1 the version consists of three design-modules with the Sync IP as part of the design.
- Xilinx low-latency mode PS DDR NV12 HDMI Audio Video Capture and Display
- This is a VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding and decoding with PS DDR for NV12 format. This module also supports single-stream audio. See the wiki page and build and run the flow of this design module.
- Xilinx low-latency mode PL DDR XV20/NV16 HDMI Video Capture and Display
- This is a VCU based HDMI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20/NV16 format. See the wiki page and build and run the flow of this design module.
- Xilinx low-latency mode PL DDR XV20 HLG SDI Audio Video Capture and Display
- This is a VCU based SDI design to showcase ultra low latency support using Sync IP, encoding with PS DDR and decoding with PL DDR for XV20 format. See the wiki page and build and run the flow of this design module.