Reset Sequence - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

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2023.1 English

The state of the VCU during PL power up and the initialization sequence for the VCU are as follows:

  • The PL is not yet configured. In this condition, the VCU is held in reset.
  • The VCU core is held in reset when the power supplies ramp up. A voltage detector present in the VCU core to PL interface keeps the core under reset while supplies ramp up.
  • PL is fully configured. The PL is configured with AXI connectivity between a CPU in the PS or PL and the AXI slave port of the VCU core. The VCU core reset can be released so that the core is in a known state.

After the VCU core reset is deasserted, use the software to program the VCU PLL for generating the clocks for VCU core and MCU blocks. When programming the VCU PLL, follow the steps described in PLL Integer Divider Programming for programming PLL configuration parameters. The PLL lock status is indicated by VCU_SLCR. For additional information, see the Zynq UltraScale+ Device Register Reference (UG1087).

Note: The VCU core clocks are available while the reset is released. The PL should be configured before releasing the raw reset, which can be controlled by the PMU from outside of the VCU core.

Additional initialization is done by software through programming the VCU core registers after the PL is configured and core is in a reset release state.

It is not possible to power down VCU rail (VCUINT_VCU) dynamically during runtime.