Reset - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

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Release Date
2023.1 English

The VCU hard block can be held under reset under the following conditions:

  • When external reset input vcu_resetn signal is asserted.
  • During PL configuration.
  • When the VCU to PL isolation is not removed.

The VCU reset signal must be asserted for, at least, two clock cycles of the VCU PLL reference clock (the slowest clock input to the VCU). The VCU registers can be accessed after the reset signal is de-asserted.

  • If software resets the VCU block in the middle of a frame, use the software to clear the physical memory allocated for the VCU.
  • The reset does not need to be asserted between changes to the VCU configuration during run-time via the VCU control software.
  • The vcu_resetn signal of Zynq UltraScale+ VCU should be tied to either AXI GPIO or ZynqMP GPIO(EMIO).

The software can program the VCU_GASKET_INIT register at offset 0x41074 in the VCU_SLCR to assert a reset pulse to the VCU block. Reset VCU using the following procedure:

  1. Ensure there is no pending AXI transaction in VCU AXI bus/AXI4-Lite bus. This can be ensured by making sure that the software that uses VCU is not running. No master should be sending any requests to VCU.
  2. Assert vcu_resetn through an EMIO GPIO pin to VCU LogiCORE IP.
  3. De-assert vcu_resetn.
  4. Write 0 to VCU gasket isolation register VCU_GASKET_INIT[1] to assert reset to VCU.
  5. Write 0 to VCU gasket isolation register VCU_GASKET_INIT[0] to enable VCU gasket isolation.
  6. Power down VCU supply.

The PLL in the VCU core can be reset through VCU_SLCR register which is accessible through AXI4-Lite interface.

Each of the encoder and decoder blocks have register-based soft reset.