Requirements - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
Release Date
2023.1 English


  • Must use a differential I/O standard
  • Must be in the same I/O column as the memory interface
  • Must be in the same SLR of memory interface for the SSI technology devices
  • The I/O standard and termination scheme are system dependent. For more information, refer to the UltraScale Architecture SelectIO Resources User Guide (UG571).


  • MMCM is used to generate the FPGA logic system clock (1/4 of the memory clock)
  • Must be located in the center bank of memory interface
  • Must use internal feedback
  • Input clock frequency divided by input divider must be 70 MHz (CLKINx / D = 70 MHz)
Table 1. Memory Part Data Rate and Frequency
Memory Part Data Rate (MT/s) Phy_clk/User_clk
KVR21SE15S8/4 2133 267 MHz
KVR21SE15S8/4 2400 300 MHz
MT40A256M16GE-075E 2400 300 MHz
MT40A256M16H A-093 2133 267 MHz
MT40A512M8HX -093 2133 267 MHz
MTA4ATF51264H Z-2G6 2133 267 MHz
MT40A1G8SA-075:E 2400 300 MHz
MT40A1G8SA-075:E 2667 333 MHz
MT40A256M16LY-062E:F 2400 300 MHz

Input Clock Period Jitter

  • Clock input period jitter must be 50 ps peak-to-peak

BUFGs and Clock Roots

  • One BUFG is used to generate the system clock to FPGA logic and another BUFG is used to divide the system clock by two.
  • BUFGs and clock roots must be located in center most bank of the memory interface.
    • For two bank systems, banks with more number of bytes selected is chosen as the center bank. If the same number of bytes is selected in two banks, then the top bank is chosen as the center bank.
    • For four bank systems, either of the center banks can be chosen. DDR4 SDRAM refers to the second bank from the top-most selected bank as the center bank.
    • Both the BUFGs must be in the same bank.


An asynchronous reset (sys_rst) input is provided. This is an active-Low reset and the sys_rst must assert for a minimum pulse width of 5 ns. The sys_rst can be an internal or external pin.

For more information on reset, see Reset Sequence.

Note: The best possible calibration results are achieved when the FPGA activity is minimized from the release of this reset input until the memory interface is fully calibrated as indicated by the init_calib_complete port (see the User Interface section of this document)