Producer AXI Ports - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID

PG252

Release Date

2023-05-16

Version

2023.1 English

Table 1. Producer AXI Write PortX Interface
Signal	Direction	Description
Write Address Channel
s_axi_mm_p_x_awid[3:0]	Input
s_axi_mm_p_x_awaddr [63:0]	Input	Byte address
s_axi_mm_p_x_awlen [7:0]	Input	Length of burst (number of transfer minus 1)
s_axi_mm_p_x_awsize [2:0]	Input	Transfer width: 000: 8-bit 001: 16-bit 010: 32-bit 011: 64-bit
s_axi_mm_p_x_awburst [1:0]	Input	Burst type: 00: Fixed 01: Incremental 10: Wrapping 11: Reserved
s_axi_mm_p_x_awvalid	Input
s_axi_mm_p_x_awready	Input
s_axi_mm_p_x_awcache[3:0]	Input
s_axi_mm_p_x_awlock	Input
s_axi_mm_p_x_awprot[2:0]	Input
s_axi_mm_p_x_awqos[3:0]	Input
s_axi_mm_p_x_awregion[3:0]	Input
S_axi_mm_p_x_awuser	Input
Write Data Channel
s_axi_mm_p_x_wdata [127:0]	Input	Read data
s_axi_mm_p_x_wstrb [15:0]	Input	Byte enable
s_axi_mm_p_x_wlast	Input	Not used by the port
s_axi_mm_p_x_wvalid	Input
s_axi_mm_p_x_wready	Input
s_axi_mm_p_x_wuser	Input
Write Response Channel
s_axi_mm_p_x_bid[3:0]	Input
s_axi_mm_p_x_bresp[1:0]	Input	Tied to zero (OKAY)
s_axi_mm_p_x_bvalid	Input
s_axi_mm_p_x_bready	Input
s_axi_mm_p_x_buser	Input

Table 2. Producer AXI Read PortX Interface
Signal	Direction	Description
Read Address Channel
s_axi_mm_p_x_arid[3:0]	Input
s_axi_mm_p_x_araddr [63:0]	Input	Byte address
s_axi_mm_p_x_arlen[7:0]	Input	Length of burst (number of transfer minus 1)
s_axi_mm_p_x_arsize[2:0]	Input	Transfer width: 000: 8-bit 001: 16-bit 010: 32-bit 011: 64-bit
s_axi_mm_p_x_arburst[1:0]	Input	Burst type: 00: Fixed 01: Incremental 10: Wrapping 11: Reserved
s_axi_mm_p_x_arvalid	Input
s_axi_mm_p_x_arready	Input
s_axi_mm_p_x_arcache[3:0]	Input
s_axi_mm_p_x_arlock	Input
s_axi_mm_p_x_arprot[2:0]	Input
s_axi_mm_p_x_arqos[3:0]	Input
s_axi_mm_p_x_arregion[3:0]	Input
s_axi_mm_p_x_aruser	Input
Read Data Channel
s_axi_mm_p_x_rid[3:0]	Input
s_axi_mm_p_x_rdata[127:0]	Input	Read data
s_axi_mm_p_x_rresp[1:0]	Input	Tied to zero (OKAY)
s_axi_mm_p_x_rlast	Input
s_axi_mm_p_x_rvalid	Input
s_axi_mm_p_x_rready	Input
s_axi_mm_p_x_ruser	Input