AXI Clock Port/Reset Port Connection
The following figure shows the block diagram of the VCU Sync IP core that has seven input AXI ports and two output AXI ports.
- S_AXI_CTRL_ACLK/S_AXI_MM_ALCLK/S_AXI_MM_P_ACLK
- The AXI ports work with respect to this clock and reset. The clock frequency used for the Sync IP is 300 MHz.
- S_AXI_CTRL_ARESETN/S_AXI_CTRL_MM_ARESETN/S_AXI_CTRL_MM_P_ARESETN
- An active-Low reset is used in the Sync IP.
Figure 1. Sync IP
