PLL Overview - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
Release Date
2023.1 English

The VCU core has a PLL for generating encoder and decoder block clocks. Typically, the PLL has an external source such as an Si570 XO programmable clock generator connected directly using an IBUFDS to the PLL reference clock. Alternatively, the IBUFDS may drive an MMCM to enable other modules to share an external clock source while meeting the sub-100ps jitter specification. It is not recommended to use the PS PLL as a clock source due to jitter requirements. The range of the PLL reference clock is 27 MHz to 60 MHz. The PLL generates a high frequency clock that can be divided down to generate various output clock frequencies. The divided clock can be supplied to the encoder block, decoder block, and MCU (separate MCU for video encoder and decoder).