Mapping for AXI Ports - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English
Table 1. Encoder Mapping of AXI Ports
Sync IP Ports Connected to Ports
S_AXI_CTRL Register Configuration – Connected to MPSoC/Arm
S_AXI_MM_P0 Producer 0 (Video Capture VDMA) Snoop Bus
S_AXI_MM_P1 Producer 1 (Video Capture VDMA) Snoop Bus
S_AXI_MM_P2 Producer 2 (Video Capture VDMA) Snoop Bus
S_AXI_MM_P3 Producer 3 (Video Capture VDMA) Snoop Bus
S_AXI_MM_0 Consumer Input 0 (VCU Encoder0)
S_AXI_MM_1 Consumer Input 1 (VCU Encoder1)
M_AXI_MM_0 Consumer Output 0 to Memory
M_AXI_MM_1 Consumer Output 1 to Memory
Table 2. Decoder Mapping of AXI Ports
Sync IP Ports Connected to Ports
S_AXI_CTRL Register Configuration; Connected to MPSoC/Arm
S_AXI_MM_P0 Producer 0 (VCU Decoder 0) Snoop Bus
S_AXI_MM_P1 Producer 1 (VCU Decoder 1) Snoop Bus
S_AXI_MM_0 Consumer 0 (Video Sink VDMA)
S_AXI_MM_1 Consumer 1 (Video Sink VDMA)
M_AXI_MM_0 To Memory
M_AXI_MM_1 To Memory