Interfacing the Core with Zynq UltraScale+ MPSoC Devices - 2023.1 English

To integrate the VCU core into an IP integrator (IPI) block design, follow these steps:

1. Launch the Vivado IDE and create a new project.
   
   
2. Click Next on New Project wizard until you reach the Family Selection window.
3. Select a target device for the VCU core.
   
   
4. Click on the Project Settings window. Click Implementation.
   
   
5. In the Settings window, enable the Performance Explore option by selecting Settings > Implementation > Options > Strategy: Performance_Explore See the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) for more information.
6. Click Create Block Design.
7. Click Add IP and type VCU. The following IP appears.
   
   
8. Add Zynq UltraScale+ VCU to the block design.
9. Add Zynq UltraScale+ MPSoC IP to the block design as shown.
   
   
10. Configure Zynq UltraScale+ MPSoC to enable AXI slave interfaces, clocking, and PL-PS interrupt signal per your design requirements. Refer to the Zynq UltraScale+ MPSoC Processing System LogiCORE IP Product Guide (PG201) for configuration options of the Zynq UltraScale+ MPSoC IP.

    The following figure shows an example of configuring the PS-PL interface signals.

11. Select PL1 clock frequency as 300 MHz.
    
    
12. Enable IRQ0 [0-7] and enable the following master, slave interfaces as shown in figure below. Also set the data width of S_AXI_HPC0_FPD to 32 bits.