Encoder Block Register Overview - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

The following table lists the encoder block registers. For additional information, see Zynq UltraScale+ Device Register Reference (UG1087).

Table 1. Encoder Registers
Register Offset Width Type Reset Value Description
MCU_RESET 0x9000 32 mixed 1 0x00000000 MCU Subsystem Reset
MCU_RESET_MODE 0x9004 32 mixed 1 0x00000001 MCU Reset Mode
MCU_STA 0x9008 32 mixed 1 0x00000000 MCU Status
MCU_WAKEUP 0x900C 32 mixed 1 0x00000000 MCU Wake-up
MCU_ADDR_OFFSET_IC0 0x9010 32 rw 0x00000000 MCU Instruction Cache Address Offset 0
MCU_ADDR_OFFSET_IC1 0x9014 32 rw 0x00000000 MCU Instruction Cache Address Offset 1
MCU_ADDR_OFFSET_DC0 0x9018 32 rw 0x00000000 MCU Data Cache Address Offset 0
MCU_ADDR_OFFSET_DC1 0x901C 32 rw 0x00000000 MCU Data Cache Address Offset 1
ITC_MCU_IRQ 0x9100 32 mixed 1 0x00000000 MCU Interrupt Trigger
ITC_CPU_IRQ_MSK 0x9104 32 rw 0x00000000 CPU Interrupt Mask
ITC_CPU_IRQ_CLR 0x9108 32 mixed 1 0x00000000 CPU Interrupt Clear
ITC_CPU_IRQ_STA 0x910C 32 mixed 1 0x00000000 CPU Interrupt Status
AXI_BW 0x9204 32 rw 0x00000000 AXI Bandwidth Measurement Window
AXI_ADDR_OFFSET_IP 0x9208 32 rw 0x00000000 Video Data Address Offset
AXI_RBW0 0x9210 32 ro 0x00000000 AXI Read Bandwidth Status 0
AXI_RBW1 0x9214 32 ro 0x00000000 AXI Read Bandwidth Status 1
AXI_WBW0 0x9218 32 ro 0x00000000 AXI Write Bandwidth Status 0
AXI_WBW1 0x921C 32 ro 0x00000000 AXI Write Bandwidth Status 1
AXI_RBL0 0x9220 32 rw 0x00000000 AXI Read Bandwidth Limiter 0
AXI_RBL1 0x9224 32 rw 0x00000000 AXI Read Bandwidth Limiter 1
  1. Mixed registers are registers that have read only, write only, and read write bits grouped together.