Enabling PL-DDR for VCU - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

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Release Date
2023.1 English

Use-case 1 (UC1) refers to the multimedia pipeline, where decoder and encoder are using PS_DDR for buffer allocations and memory read/write operations of video processing. The current system is capable of encoding and decoding of 4k@60 fps and transcoding of 4k@30 fps with the available bandwidth of PS_DDR. The target is to achieve transcoding at 4k@60fps and it has been identified that the PS_DDR bandwidth is the bottleneck. A new design has been proposed to overcome PS_DDR bandwidth limitations.

Use-case 2 (UC2) is the new design approach proposed to use PL_DDR for decoding and PS_DDR for encoding, so that the DDR bandwidth would be sufficient to achieve transcoding at 4k@60fps. The figure below explains the transcoding pipeline. The decoder completes the decoding process and writes the data to PL_DDR and the same is copied to PS_DDR from where the encoder consumed the data. The buffer copy from PL_DDR to PS_DDR is achieved by DMA transfers.

2 GB Access Limit

The following access limits apply:

  • VCU IP can access 4 GB range from aligned 4 GB base address and MCU can access buffers within 2 GB range only from dcache offset.
  • The MCU requires a certain buffer access during encode/decode process, so the buffers that are accessed by MCU should be within 2 GB range from dcache offset.
    Figure 1. Use Case 2