DDR4 DSDRAM Feature Summary - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
Release Date
2023.1 English
Important: Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP can only be used with the H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoCs.
  • Supports five high performance AXI ports for connecting to decoder 0, decoder 1, MCU, PS, and display controller interface
  • Component/SODIMM support for interface width of 64-bits
    • Supports speed bins of 2133, 2400, and 2667
    • Support for Zynq-UltraScale+ EV series -1e , -2 , -3e parts and supported frequencies 2133 MT/s, 2400 MT/s, 2667 MT/s.
    • Does not support speed grades –1L and –1LV.
    • Supports AXI

    See Table 1 for a complete list of supported memories.

  • Reorders FIFO for better efficiencyx8 and x16 device support
  • 8-word burst support
  • ODT support
  • Write leveling support for DDR4 (fly-by routing topology required component designs)
  • JEDEC-compliant DDR4 initialization support
  • Encrypted source code delivery in Verilog/VHDL
  • Open, closed, and transaction based pre-charge controller policy
  • Interface calibration and training information available through the Vivado hardware manager
  • Target technologies (physical interface):
    • Using MIG generated phy-only design
    • Zynq UltraScale+ MPSoC
    • DDR4 features are supported
  • Controller:
    • High efficiency is achieved for multi-port and random access applications through
    • Reordering
    • Burst maximization
    • Deep lookahead
    • Ping pong ss
    • High frequency can be achieved through configurable pipes
    • Low resource count