Core Design Signals - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)
Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

The following table shows the signals to be used while designing the core and their descriptions:

Table 1. Core Design Signals
Signal Description
phy_Clk These are the clock rates that are set for each of the memory speed bins:
  • For 2133 speed grade, the usrclk is 267
  • For 2400 speed grade, usrclk is 300
  • For 2667 speed grade, usrclk is 333
Note: phy_Clk was Usrclk in 2019.1 and earlier releases.
phy_sRst This signal specifies that the DDR controller is out of reset (based on MMCM locked signal in VCU DDR4 controller) and it can be used to gate interconnect reset signal.
Note: phy_sRst was sRst_out in 2019.1 and earlier releases.
InitDone This signal specifies DDR4 calibration completion.
Note: You should handle the domain crossing in the interconnect. You can use the phy_clk as master clock for the interconnect that interfaces with DDR4 memory ports.

Endianness

BA317 ports use normally little endian convention. The following table shows accesses to same data in memory from different kind of ports.

Table 2. BA317 Ports
Port Endianness Address Data
64-bit buffered port Little endian 0x0 0x0807060504030201
32-bit buffered port Little endian 0x0 0x04030201
0x1 0x08070605
16-bit buffered port Little endian 0x0 0x0201
0x1 0x0403
0x2 0x0605
0x3 0x0807
8-bit buffered port Little endian 0x0 0x01
0x1 0x02
0x2 0x03
0x3 0x04
0x4 0x05
0x5 0x06
0x6 0x07
0x7 0x08
128-bit AXI port Little endian 0x0 0x100F0E0D0C0B0A090807060504030201
32-bit AXI port Little endian 0x0 0x04030201
0x1 0x08070605

Physical Interface

The following table lists all available physical interfaces with the supported SDRAM and FPGA devices. Some additional FPGAs might be supported because they are compatible with the listed FPGAs.

Table 3. Physical Interface
Phy SDRAM FPGA Rate
phyXilinxUltrascale DDR4 Zynq-UltraScale+ EV Quad

Vendor guidelines apply.

UltraScale/UltraScale+ Xilinx Phy (phyXilinxUltrascale)

Refer to the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) for details.