Signal | Direction | Description |
---|---|---|
Write Address Channel | ||
s_axi_mm_x_awid[3:0] | Input | |
s_axi_mm_x_awaddr [63:0] | Input | Byte address |
s_axi_mm_x_awlen [7:0] | Input | Length of burst (number of transfer minus 1) |
s_axi_mm_x_awsize [2:0] | Input | Transfer width:
|
s_axi_mm_x_awburst [1:0] | Input | Burst type
|
s_axi_mm_x_awvalid | Input | |
s_axi_mm_x_awready | Output | |
s_axi_mm_x_awcache[3:0] | Input | |
s_axi_mm_x_awlock | Input | |
s_axi_mm_x_awprot[2:0] | Input | |
s_axi_mm_x_awqos[3:0] | Input | |
s_axi_mm_x_awregion[3:0] | Input | |
s_axi_mm_x_awuser | Input | |
Write Data Channel | ||
s_axi_mm_x_wdata [127:0] | Input | Write data |
s_axi_mm_x_wstrb [15:0] | Input | Byte enable |
s_axi_mm_x_wlast | Input | Not used by the port |
s_axi_mm_x_wvalid | Input | |
s_axi_mm_x_wready | Output | |
s_axi_mm_x_wuser | Input | |
Write Response Channel | ||
s_axi_mm_x_bid[3:0] | Output | |
s_axi_mm_x_bresp[1:0] | Output | Tied to zero (OKAY) |
s_axi_mm_x_bvalid | Output | |
s_axi_mm_x_bready | Input | |
s_axi_mm_x_buser | Output |
Signal | Direction | Description |
---|---|---|
Read Address Channel | ||
s_axi_mm_x_arid[3:0] | Input | |
s_axi_mm_x_araddr [63:0] | Input | Byte address |
s_axi_mm_x_arlen[7:0] | Input | Length of burst (number of transfers minus 1) |
s_axi_mm_x_arsize[2:0] | Input | Transfer width:
|
s_axi_mm_x_arburst[1:0] | Input | Burst type:
|
s_axi_mm_x_arvalid | Input | |
s_axi_mm_x_arready | Output | |
s_axi_mm_x_arcache[3:0] | Input | |
s_axi_mm_x_arlock | Input | |
s_axi_mm_x_arprot[2:0] | Input | |
s_axi_mm_x_arqos[3:0] | Input | |
s_axi_mm_x_arregion[3:0] | Input | |
s_axi_mm_x_aruser | Input | |
Read Data Channel | ||
s_axi_mm_x_rid[3:0] | Output | |
s_axi_mm_x_rdata[127:0] | Output | Read Data |
s_axi_mm_x_rresp[1:0] | Output | Tied to zero (OKAY) |
s_axi_mm_x_rlast | Output | |
s_axi_mm_x_rvalid | Output | |
s_axi_mm_x_rready | Input | |
s_axi_mm_x_ruser | Output |