Common Interface Signals - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

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2023.1 English

The following table summarizes the signals which are either shared by, or not part of the dedicated AXI4 interfaces.

Table 1. VCU Ports
Port Name Direction Description
m_axi_enc_aclk Input AXI clock input for M_AXI_VCU_ENCODER0 and M_AXI_VCU_ENCODER1
s_axi_lite_aclk Input AXI clock input for S_AXI_PL_VCU_LITE
pll_ref_clk Input PLL reference clock input
vcu_resetn Input Active-Low reset input from PL
vcu_host_interrupt Output Active-High interrupt output from VCU. Can be mapped to PL-PS interrupt pin.
m_axi_dec_aclk Input AXI input clock for M_AXI_VCU_DECODER0 and M_AXI_VCU_DECODER1
m_axi_mcu_aclk Input Input clock for M_AXI_MCU interface