The table below lists the user-configurable PS eFUSE parameters for Zynq UltraScale+ MPSoC devices.
| Macro Name | Description |
|---|---|
| XSK_EFUSEPS_AES_RD_LOCK | Default = FALSE TRUE permanently disable the CRC check of FUSE_AES. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_AES_WR_LOCK | Default = FALSE TRUE permanently disable the writing to FUSE_AES block. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_ENC_ONLY | Default = FALSE TRUE permanently enable encrypted booting only using the Fuse key. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_BBRAM_DISABLE | Default = FALSE TRUE permanently disable the BBRAM key. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_ERR_DISABLE | Default = FALSE TRUE permanently disables the error messages in JTAG status register. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_JTAG_DISABLE | Default = FALSE TRUE permanently disable JTAG controller. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_DFT_DISABLE | Default = FALSE TRUE permanently disable DFT boot mode. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_PROG_GATE_DISABLE | Default = FALSE TRUE permanently disable PROG_GATE feature in PPD. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_SECURE_LOCK | Default = FALSE TRUE permanently disable reboot into JTAG mode when doing a secure lockdown. FALSE does not modify thi s control bit of eFuse. |
| XSK_EFUSEPS_RSA_ENABLE | Default = FALSE TRUE permanently enable RSA authentication during boot. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_PPK0_WR_LOCK | Default = FALSE TRUE permanently disable writing to PPK0 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_PPK0_INVLD | Default = FALSE TRUE permanently revoke PPK0. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_PPK1_WR_LOCK | Default = FALSE TRUE permanently disable writing PPK1 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_PPK1_INVLD | Default = FALSE TRUE permanently revoke PPK1. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_0 | Default = FALSE TRUE permanently disable writing to USER_0 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_1 | Default = FALSE TRUE permanently disable writing to USER_1 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_2 | Default = FALSE TRUE permanently disable writing to USER_2 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_3 | Default = FALSE TRUE permanently disable writing to USER_3 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_4 | Default = FALSE TRUE permanently disable writing to USER_4 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_5 | Default = FALSE TRUE permanently disable writing to USER_5 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_6 | Default = FALSE TRUE permanently disable writing to USER_6 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_USER_WRLK_7 | Default = FALSE TRUE permanently disable writing to USER_7 efuses. FALSE does not modify this control bit of eFuse. |
| XSK_EFUSEPS_LBIST_EN | Default = FALSE TRUE permanently enables logic BIST to be run during boot. FALSE does not modify this control bit of eFUSE. |
| XSK_EFUSEPS_LPD_SC_EN | Default = FALSE TRUE permanently enables zeroization of registers in Low Power Domain(LPD) during boot. FALSE does not modify this control bit of eFUSE. |
| XSK_EFUSEPS_FPD_SC_EN | Default = FALSE TRUE permanently enables zeroization of registers in Full Power Domain(FPD) during boot. FALSE does not modify this control bit of eFUSE. |
| XSK_EFUSEPS_PBR_BOOT_ERR | Default = FALSE TRUE permanently enables the boot halt when there is any PMU error. FALSE does not modify this control bit of eFUSE. |