Flush a level 2 cache line.
If the byte specified by the address (adr) is cached by the L2 cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.
Note: The bottom 4 bits are set to 0, forced by architecture.
Prototype
void Xil_L2CacheFlushLine(u32 adr);Parameters
The following table lists the Xil_L2CacheFlushLine function arguments.
| Name | Description |
|---|---|
| adr | 32-bit address of the data/instruction to be flushed. |