Store a level 1 Data cache line.
If the byte specified by the address (adr) is cached by the Data cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory. After the store completes, the cacheline is marked as unmodified (not dirty).
Note: The bottom 5 bits are set to 0, forced by architecture.
Prototype
void Xil_L1DCacheStoreLine(u32 adr);Parameters
The following table lists the Xil_L1DCacheStoreLine function arguments.
| Name | Description |
|---|---|
| adr | Address to be stored. |