Xil_L1DCacheFlushLine - 2023.1 English

Standalone Library Documentation: BSP and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2023-05-16
Version
2023.1 English

Flush a level 1 Data cache line.

If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.

Note: The bottom 5 bits are set to 0, forced by architecture.

Prototype

void Xil_L1DCacheFlushLine(u32 adr);

Parameters

The following table lists the Xil_L1DCacheFlushLine function arguments.

Table 1. Xil_L1DCacheFlushLine Arguments
Name Description
adr 32-bit address of the data to be flushed.

Returns

None.