Performance - 2023.1 English

Standalone Library Documentation: BSP and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2023-05-16
Version
2023.1 English

Performance metrics for the XilSEM library are derived from silicon specifications and direct measurement and are for budgetary purposes only. Actual performance might vary.

Table 1. Performance Metrics for the Configuration RAM
Device and Conditions Initialization Complete Scan Time Correctable ECC Error Handling Uncorrectable CRC Error Handling Other Uncorrectable Error Handling

XCVC1902

  • PMC = 320 MHz
  • CFU = 400 MHz

SW ECC: 18.1 ms

HW ECC: 36.2 ms

13.6 ms (with 149682 CRAM frames) 55 μs 16 μs 49 μs

XCVM1802

  • PMC = 320 MHz
  • CFU = 400 MHz

SW ECC: 18.1 ms

HW ECC: 36.2 ms

13.6 ms (with 149682 CRAM frames) 55 μs 16 μs 49 μs
Table 2. Performance Metrics for NPI Registers
Device and Conditions Initialization Complete Scan Time Uncorrectable SHA Error Handling Other Uncorrectable Error Handling

XCVC1902

  • PMC = 320 MHz
  • CFU = 400 MHz

SW SHA: 13.2 ms

HW SHA: 13.2 ms

13.3 ms (with 900+ NPI slaves) 12.47 ms 342.8 s (DMA to SHA transfer timeout)

XCVM1802

  • PMC = 320 MHz
  • CFU = 420 MHz

SW SHA: 14.7 ms

HW SHA: 14.7 ms

14.7 ms (with 900+ NPI slaves) 13.7 ms 353.5 s (DMA to SHA transfer timeout)
Table 3. Performance Metrics for the CRAM scan with different clock frequencies (XCVC1902)
Device and Conditions (XCVC1902) CRAM Scan Frequency Initialization Complete Scan Time (Total Frames: 149682) Correctable ECC Error Handling Uncorrectable CRC Error Handling Other Uncorrectable Error Handling

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 3

399.96 MHz

HWECC: 27.044 ms

SWECC: 13.619 ms

13.84 ms 59 μs 16 μs 44 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 4

299.96 MHz

HWECC: 36.024 ms

SWECC: 18.145 ms

18.46 ms 63 μs 16 μs 48 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 5

239.96 MHz

HWECC: 45.022 ms

SWECC: 22.591 ms

23.08 ms 68 μs 17 μs 50 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 6

199.98 MHz

HWECC: 53.672 ms

SWECC: 22.087 ms

27.69 ms 70 μs 18 μs 53 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 7

171.41 MHz

HWECC: 63.078 ms

SWECC: 31.845 ms

32.3 ms 75 μs 19 μs 57 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 8

149.98 MHz

HWECC: 72.117 ms

SWECC: 36.378 ms

36.92 ms 79 μs 19 μs 59 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 9

133.32 MHz

HW ECC: 81.276 ms

SWECC: 40.918 ms

41.54 ms 83 μs 20 μs 63 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 10

119.98 MHz

HWECC: 90.203 ms

SWECC: 45.473 ms

46.15 ms 87 μs 21 μs 66 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 11

109.08 MHz

HWECC: 99.289 ms

SWECC: 50.033 ms

50.77 ms 89 μs 22 μs 68 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 12

99.99 MHz

HWECC: 108.278 ms

SWECC: 54.536 ms

55.38 ms 95 μs 22 μs 72 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 13

92.29 MHz

HWECC: 117.260 ms

SWECC: 59.059 ms

60.00 ms 97 μs 23 μs 73 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 14

85.7 MHz

HWECC: 125.280 ms

SWECC: 63.617 ms

64.61 ms 101 μs 24 μs 78 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 15

79.99 MHz

HWECC: 135.362 ms

SWECC: 68.207 ms

69.23 ms 108 μs 25 μs 81 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 16

74.99 MHz

HWECC: 143.257 ms

SWECC: 72.739 ms

73.85 ms 109 μs 25 μs 81 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 17

70.58 MHz

HWECC: 153.441 ms

SWECC: 77.297 ms

78.46 ms 112 μs 23 μs 85 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 18

66.66 MHz

HWECC: 162.451 ms

SWECC: 81.809 ms

83.08 ms 118 μs 27 μs 89 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 19

63.15 MHz

HWECC: 169.972 ms

SWECC: 86.382 ms

87.69 ms 122 μs 28 μs 93 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 20

59.99 MHz

HWECC: 178.952 ms

SWECC: 90.844 ms

92.31 ms 127 μs 28 μs 96 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 21

57.13 MHz

HWECC: 189.504 ms

SWECC: 95.403 ms

96.92 ms 129 μs 30 μs 98 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 25

47.99 MHz

HWECC: 226.884 ms

SWECC: 113.603 ms

115.39 ms 147 μs 33 μs 111 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 30

39.99 MHz

HWECC: 268.404 ms

SWECC: 136.369 ms

138.469 ms 170 μs 37 μs 129 μs

PMC = 320 MHz

FBDIV = 72

Input_clock = 33.33 MHz

CLKOUTDIV = 2

DIVISOR0 = 32

37.49 MHz

HWECC: 286.474 ms

SWECC: 145.374 ms

147.7 ms 172 μs 38 μs 130 μs

Error detection latency is the major component of the total error mitigation latency. Error detection latency is a function of the device size and the underlying clock signals driving the processes involved, as these determine the Complete Scan time. It is also a function of the type of error and the relative position of the error with respect to the position of the scan process, at the time the error occurs. The error detection latency can be bounded as follows:

  • Maximum error detection latency for detection by ECC is one Complete Scan Time
    • This represents a highly unlikely case when an error at a given location occurs directly “behind” the scan process.
    • It will take one Complete Scan Time for the scan process to return to the error location at which time it will detect it.
  • Maximum error detection latency for detection by CRC or SHA is 2.0 × Complete Scan Time
    • This represents an extremely unlikely case when an error occurs directly “behind” the scan process and is located at the scan start location (where the checksum accumulation begins at each scan).
    • It will take one Complete Scan Time for the scan process to complete the current checksum accumulation (which will pass) and then a second Complete Scan Time to complete a checksum accumulation which includes the error (which will fail).

When a CFRAME error is detected, a task is added to PLM scheduler for error validation, correction and notification. The time for correction and notification depends on other requests which PLM has already been processing. The time also depends on the secure data size and secure operation. The following table lists the timing for different secure operations and power management tasks.

Table 4. PLM requests processing time
Example PLM Requests/Tasks1 Processing Time (Approximate)
Optional NPI Scan (varies by resource utilization) 15 ms
Secure Data Request Authentication (RSA)

Xsecure_RsaPublicEncrypt_64bit

1.87 ms
Secure Data Request Authentication (RSA)

Xsecure_RsaPrivateDecrypt_64bit

91.13 ms
Secure Data Request Authentication (ECDSA-P384)

Xsecure_EllipticVerifySign_64bit

6.31 ms
Secure Data Request Authentication (ECDSA-P521)

Xsecure_EllipticVerifySign_64bit

14.56 ms
Secure Data Request, SHA, 100 Kb (varies by size) 0.17 ms
Secure Data Request, AES, 100 Kb (varies by size) 0.77 ms
Power Management Requests (estimated) 1 ms
1 DFX activity requires XilSEM scan to be stopped (same as Legacy SEM IP core) to avoid scan interference with each other. Clock management request estimates are pending, time is assumed short.