The Xilinx adapters for EMAC/GigE cores are configurable.
Ethernetlite Adapter Options
The following table describes the configuration parameters for the axi_ethernetlite adapter.
| Attribute | Description | Type | Default |
|---|---|---|---|
| sw_rx_fifo_size | Software Buffer Size in bytes of the receive data between EMAC and processor | integer | 8192 |
| sw_tx_fifo_size | Software Buffer Size in bytes of the transmit data between processor and EMAC | integer | 8192 |
TEMAC Adapter Options
The following table describes the configuration parameters for the axi_ethernet and GigE
adapters.
| Attribute | Type | Description |
|---|---|---|
| n_tx_descriptors | integer | Number of TX descriptors to be used. For high performance systems there might be a need to use a higher value. Default is 64. |
| n_rx_descriptors | integer | Number of RX descriptors to be used. For high performance systems there might be a need to use a higher value. Typical values are 128 and 256. Default is 64. |
| n_tx_coalesce | integer | Setting for TX interrupt coalescing. Default is 1. |
| n_rx_coalesce | integer | Setting for RX interrupt coalescing. Default is 1. |
| tcp_rx_checksum_offload | boolean | Offload TCP Receive checksum calculation (hardware support required). For GigE in Zynq devices, Zynq UltraScale+ MPSoC, and Versal device, the TCP receive checksum offloading is always present, so this attribute does not apply. Default is false. |
| tcp_tx_checksum_offload | boolean | Offload TCP Transmit checksum calculation (hardware support required). For GigE cores (Zynq devices, Zynq UltraScale+ MPSoC, and Versal device), the TCP transmit checksum offloading is always present, so this attribute does not apply. Default is false. |
| tcp_ip_rx_checksum_ofload | boolean | Offload TCP and IP Receive checksum calculation (hardware support required). Applicable only for AXI systems. For GigE in Zynq devices, Zynq UltraScale+ MPSoC, and Versal ACAP, the TCP and IP receive checksum offloading is always present, so this attribute does not apply. Default is false. |
| tcp_ip_tx_checksum_ofload | boolean | Offload TCP and IP Transmit checksum calculation (hardware support required). Applicable only for AXI systems. For GigE in Zynq, Zynq UltraScale+ MPSoC, and Versal ACAP, the TCP and IP transmit checksum offloading is always present, so this attribute does not apply. Default is false. |
| phy_link_speed | CONFIG_LINKSPEED_ AUTODETECT | Link speed as auto-negotiated by the PHY. lwIP configures the TEMAC/GigE for this speed setting. This setting must be correct for the TEMAC/GigE to transmit or receive packets. The CONFIG_LINKSPEED_ AUTODETECT setting attempts to detect the correct linkspeed by reading the PHY registers; however, this is PHY dependent, and has been tested with the Marvell and TI PHYs present on the AMD development boards. For other PHYs, select the correct speed. Default is enum. |
| temac_use_jumbo_ frames_experimental | boolean | Use TEMAC jumbo frames (with a size up to 9k bytes). If this option is selected, jumbo frames are allowed to be transmitted and received by the TEMAC. For GigE in Zynq devices, there is no support for jumbo frames, so this attribute does not apply. Default is FALSE. |