Pixel-Wise Addition - 2023.1 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.1 English

The add function performs the pixel-wise addition between two input images and returns the output image.

Iout(x, y) = Iin1(x, y) + Iin2(x, y)

Where:

  • Iout(x, y) is the intensity of the output image at (x, y) position
  • Iin1(x, y) is the intensity of the first input image at (x, y) position
  • Iin2(x, y) is the intensity of the second input image at (x, y) position.

XF_CONVERT_POLICY_TRUNCATE: Results are the least significant bits of the output operand, as if stored in two’s complement binary format in the size of its bit-depth.

XF_CONVERT_POLICY_SATURATE: Results are saturated to the bit depth of the output operand.

API Syntax

template<int POLICY_TYPE, int SRC_T, int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void add (
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> src1,
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_2> src2,
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> dst )

Parameter Descriptions

The following table describes the template and the function parameters.

Table 665 Table . add Parameter Description
Parameter Description
POLICY_TY PE Type of overflow handling. It can be either, XF_CONVERT_POLICY_SATURATE or XF_CONVERT_POLICY_TRUNCATE.
SRC_T Pixel type. Options are XF_8UC1, XF_8UC3, XF_16SC3, and XF_16SC1.
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image (must be a multiple of 8, for 8-pixel operation)
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1 Depth of the input image.
XFCVDEPTH_IN_2 Depth of the input image.
XFCVDEPTH_OUT_1 Depth of the output image.
src1 Input image
src2 Input image
dst Output image

Resource Utilization

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.

Table 666 Table . add Function Resource Utilization Summary
Operating Mode

Operating Frequency

(MHz)

 Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 pixel 300 0 0 62 55 11
8 pixel 150 0 0 65 138 24

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process 4K image with 3 channels.

Table 667 Table . add Function Resource Utilization Summary
Operating Mode

Operating Frequency

(MHz)

 Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 pixel 300 0 0 113 77 24

Performance Estimate

The following table summarizes the performance in different configurations, as generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.

Table 668 Table . add Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7