pyrUp
function is an image up-sampling algorithm. It first
inserts zero rows and zero columns after every input row and column
making up to the size of the output image. The output image size is
always . The zero padded image is then smoothened using
Gaussian image filter. Gaussian filter for the pyramid-up function
uses a fixed filter kernel as given below:However, to make up for the pixel intensity that is reduced due to zero padding, each output pixel is multiplied by 4.
API Syntax
template<int TYPE, int ROWS, int COLS, int NPC, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>
void pyrUp (xf::cv::Mat<TYPE, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src, xf::cv::Mat<TYPE, ROWS, COLS, NPC, XFCVDEPTH_OUT> & _dst)
Parameter Descriptions
The following table describes the template and the function parameters.
Parameter | Description |
---|---|
TYPE | Input and Output pixel type. Only 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3) |
ROWS | Maximum Height or number of output rows to build the hardware for this kernel |
COLS | Maximum Width or number of output columns to build the hardware for this kernel |
NPC | Number of pixels to process per cycle. Currently, the kernel supports only 1 pixel per cycle processing (XF_NPPC1). |
XFCVDEPTH_IN | Depth of the input image. |
XFCVDEPTH_OUT | Depth of the output image. |
_src | Input image stream |
_dst | Output image stream |
Resource Utilization
The following table summarizes the resource utilization of pyrUp for 1 pixel per cycle implementation, for a maximum input image size of 1920x1080 pixels. The results are after synthesis in Vivado HLS 2019.1 for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz.
Operating Mode | Operating Frequency (MHz) |
Utilization Estimate | |||
---|---|---|---|---|---|
LUTs | FFs | DSPs | BRAMs | ||
1 Pixel | 300 | 1124 | 1199 | 0 | 10 |
The following table summarizes the resource utilization of pyrUp for 1 pixel per cycle implementation, for a maximum input image size of 4K with BGR. The results are after synthesis in Vivado HLS 2019.1 for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz.
Operating Mode | Operating Frequency (MHz) |
Utilization Estimate | |||
---|---|---|---|---|---|
LUTs | FFs | DSPs | BRAMs | ||
1 Pixel | 300 | 2074 | 2176 | 0 | 59 |
Performance Estimate
The following table summarizes performance estimates of pyrUp function on Vivado HLS 2019.1 for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA.
Operating Mode | Operating Frequency (MHz) |
Input Image Size | Latency Estimate |
---|---|---|---|
Max (ms) | |||
1 pixel | 300 | 1920x1080 | 27.82 |