The CompareS function performs the comparison of a pixel in the input image (src1) and the given scalar value scl, and stores the result in dst.
dst(x,y)=src1(x,y) CMP_OP scalar
CMP_OP – a flag specifies correspondence between the pixel and the scalar.
- XF_CMP_EQ : src1 is equal to scl
- XF_CMP_GT : src1 is greater than scl
- XF_CMP_GE : src1 is greater than or equal to scl
- XF_CMP_LT : src1 is less than scl
- XF_CMP_LE : src1 is less than or equal to scl
- XF_CMP_NE : src1 is unequal to scl
If the comparison result is true, then the corresponding element of dst is set to 255, else it is set to 0.
API Syntax
template<int CMP_OP, int SRC_T , int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void compareS(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src1, unsigned char _scl[XF_CHANNELS(SRC_T,NPC)], xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| CMP_OP | The flag that specifying the relation between the elements to be checked |
| SRC_T | Input pixel type. 8-bit, unsigned, 1 channel is supported (XF_8UC1). |
| ROWS | Maximum height of input and output image |
| COLS | Maximum width of input and output image. In case of N-pixel parallelism, the width should be a multiple of N |
| NPC | Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixels operations respectively. |
| XFCVDEPTH_IN_1 | Depth of input image |
| XFCVDEPTH_OUT_1 | Depth of output image |
| _src1 | First input image |
| _scl | Input scalar value, the size should be number of channels |
| _dst | Output image |
Resource Utilization
The following table summarizes the resource utilization of the CompareS function with XF_CMP_NE configuration in Resource optimized (8 pixels) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA
| Name | Resource Utilization | |
|---|---|---|
| 1 pixel per clock operation | 8 pixel per clock operation | |
| 300 MHz | 150 MHz | |
| BRAM_18K | 0 | 0 |
| DSP48E | 0 | 0 |
| FF | 93 | 93 |
| LUT | 39 | 68 |
| CLB | 21 | 28 |
Performance Estimate
The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.
| Operating Mode | Latency Estimate |
|---|---|
| Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 6.9 |
| 8 pixel operation (150 MHz) | 1.7 |