template<int SRC_T,int DST_T,int ROWS,int COLS,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>void bgr2yuyv(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src,xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT> & _dst)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| SRC_T | Input pixel type. Only 8-bit, unsigned, 3-channel is supported (XF_8UC3) |
| DST_T | Output pixel type. Only 16-bit, unsigned, 1-channel is supported (XF_16UC1) |
| ROWS | Maximum height of input and output image |
| COLS | Maximum width of input and output image. Must be multiple of NPC. |
| NPC | Number of pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8.. |
| XFCVDEPTH_IN | Depth of input image |
| XFCVDEPTH_OUT | Depth of output image |
| _src | RGB/BGR input image |
| _dst | UYVY/YUYV output image |
Resource Utilization
The following table summarizes the resource utilization of RGB/BGR
to UYVY/YUYV function in normal mode(1-Pixel), as generated in the
Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA.
Operating Mode Operating Frequency (MHz) Utilization Estimate BRAM_18K DSP_48Es FF LUT CLB 1 Pixel 300 0 9 249 203 55
Performance Estimate
The following table summarizes the performance of the kernel in single pixel configuration as generated using Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.
| Operating Mode | Latency Estimate |
|---|---|
| Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 6.9 |