Resource Utilization - 2023.1 English

The hardware resources are listed in Table 155. This is for the demonstration as configured by default (two cfBSMEngine engines) achieving a 300 MHz clock rate.

Table 155 Hardware resources for single kernel with two parallel cfBSMEngine engines.

Engines	BRAM	DSP	Register	LUT	Latency	clock period(ns)
bsm_kernel	374	520	101830	80272	334	3.333