Resource Utilization - 2023.1 English

The hardware resources are listed in Table 156. This is for the demonstration as configured by default (two cfB76Engine engines) achieving a 300 MHz clock rate.

Table 156 Hardware resources for single kernel with two parallel cfB76Engine engines.

Engines	BRAM	DSP	Register	LUT	Latency	clock period(ns)
b76_kernel	374	496	77741	65491	334	3.333