Executable Usage - 2023.1 English

Vitis Libraries

Release Date
2023.1 English
  • Work Directory(Step 1)

The steps for library download and environment setup can be found in l2_vitis_graph. For getting the design,

cd L2/benchmarks/label_propagation
  • Build kernel(Step 2)

Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.

make run TARGET=hw PLATFORM=xilinx_u250_xdma_201830_2
  • Run kernel(Step 3)

To get the benchmark results, please run the following command.

./build_dir.hw.xilinx_u250_xdma_201830_2/host.exe -xclbin build_dir.hw.xilinx_u250_xdma_201830_2/LPKernel.xclbin -o data/csr_offsets.txt -i data/csr_columns.txt -label data/label.txt

Label Propagation Input Arguments:

Usage: host.exe -[-xclbin -o -i -label]
       -xclbin         label propagation binary
       -o              offset file of input graph in CSR format
       -i              edge file of input graph in CSR format
       -label          golden reference file for validatation

Note: Default arguments are set in Makefile, you can use other Datasets listed in the table.

  • Example output(Step 4)
---------------------Label Propagation----------------
Found Platform
Platform Name: Xilinx
Found Device=xilinx_u250_xdma_201830_2
INFO: Importing build_dir.hw.xilinx_u250_xdma_201830_2/LPKernel.xclbin
Loading: 'build_dir.hw.xilinx_u250_xdma_201830_2/LPKernel.xclbin'
kernel has been created
kernel start------
vertexNum=11   edgeNum=20
burstReadSplit2Strm ing
offsetCtrlIndex ing
mergeSortWrapper ing
labelProcess ing
combineStrm ing
kernel end------
Execution time 218.327ms
Write DDR Execution time 38.692 ms
Kernel Execution time 13.2172 ms
Read DDR Execution time 93.9891 ms
Total Execution time 218.276 ms
INFO: case pass!