2-Dimensional SSR FFT is built on top of 1-D SSR FFT. It deploys multiple 1-D SSR FFT processors in parallel to accelerate calculations. Potentially 2-D SSR FFT can be accelerated by deploying multiple processors in parallel, to process multiple lines(rows/columns) of input data whose 1-D SSR FFT calculation is independent of each other (Data parallelism). Essentially decreasing the latency and also increasing the throughput. But 2-D SSR FFT throughput can also be increased by using a task level pipeline where one set of 1-D SSR FFT processors also called line processors work row wise on 2-D input data and another set of line processors work column wise in a task level pipeline on data produced by row processors as shown in the figure below. The row processors perform 1-D SSR FFT row by row and column processors perform transforms on columns. Row processors connect to column processors through a matrix transposer. The following figure shows a simplified block diagram which gives the 2-D SSR FFT architecture used by the Vitis SSR FFT Library. Essentially it is a big dataflow pipeline of blocks which perform data permutations and 1-D FFT transforms working either row wise or column wise. Each of the 1-D SSR FFT processor ( 1-D Vitis SSR FFT ) is a Super Sample Rate streaming processor. The 1-D SSR FFT processors used along the rows and columns are supposed to have same configuration which is specified as described in Configuration Parameter Structure for Floating Point SSR FFT
