After synthesis, 1-D SSR FFT HLS IP maps to a processing block with stream interface at both the input and output.
If user requires a streaming 1-D SSR FFT block with FIFO interface at both the input and output, as shown in the following figure:
- Declares the input and output streams explicitly with corresponding stream depth:
// input stream of innerFFT hls::stream<I_TYPE, FIFO_DEPTH> inStrm[R]; // output stream of innerFFT hls::stream<O_TYPE, FIFO_DEPTH> outStrm[R];
- Feeds data to the input FIFO, or eats from the output one:
for (int t = 0; t < L / R; t++) { for (int r = 0; r < R; r++) { inStrm[r].write(inD[r][t]); } } for (int t = 0; t < L / R; t++) { for (int r = 0; r < R; r++) { outD[r][t] = outStrm[r].read(); } }
3. If the 1-D SSR FFT IP is facing another HLS IP in the input chain or output chain, the inner loop doing reading and writing should be unrolled.