- Work Directory(Step 1)
The steps for library download and environment setup can be found in l2_vitis_database. For getting the design,
cd L1/benchmarks/hash_semi_join
- Build kernel(Step 2)
Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.
make run TARGET=hw PLATFORM=xilinx_u280_xdma_201920_3
- Run kernel(Step 3)
To get the benchmark results, please run the following command.
./build_dir.hw.xilinx_u280_xdma_201920_3/test_join.exe -xclbin build_dir.hw.xilinx_u280_xdma_201920_3/semi_join.xclbin
Hash Semi-Join Input Arguments:
Usage: test_join.exe -xclbin
-xclbin: the kernel name
Note: Default arguments are set in Makefile, you can use other platforms to build and run.
- Example output(Step 4)
------------ TPC-H Q5 Example 2 ------------- Host map buffer has been allocated. Lineitem 6001215 rows Orders 1500000rows Lineitem table has been read from disk Orders table has been read from disk INFO: CPU ref matched 48055 rows, sum = 22623914778545 Found Platform Platform Name: Xilinx Selected Device xilinx_u280_xdma_201920_3 INFO: Importing build_dir.hw.xilinx_u280_xdma_201920_3/semi_join.xclbin Loading: 'build_dir.hw.xilinx_u280_xdma_201920_3/semi_join.xclbin' Kernel has been created DDR buffers have been mapped/copy-and-mapped FPGA result 0: 2262391477.8545 Golden result 0: 2262391477.8545 FPGA execution time of 1 runs: 18914 usec Average execution per run: 18914 usec ---------------------------------------------