- Work Directory(Step 1)
The steps for library download and environment setup can be found in l2_vitis_database. For getting the design,
cd L1/benchmarks/hash_anti_join
- Build kernel(Step 2)
Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.
make run TARGET=hw PLATFORM=xilinx_u280_xdma_201920_3
- Run kernel(Step 3)
To get the benchmark results, please run the following command.
./build_dir.hw.xilinx_u280_xdma_201920_3/test_join.exe -xclbin build_dir.hw.xilinx_u280_xdma_201920_3/hash_anti_join.xclbin
Hash anti-join Input Arguments:
Usage: test_join.exe -xclbin
-xclbin: the kernel name
- Example output(Step 4)
------------- Hash-Join Test ---------------- Data integer width is 32. Host map buffer has been allocated. Lineitem 6001215 rows Orders 227597rows Lineitem table has been read from disk Orders table has been read from disk INFO: CPU ref matched 611326 rows, sum = 288203573816672 Found Platform Platform Name: Xilinx Selected Device xilinx_u280_xdma_201920_3 INFO: Importing build_dir.hw.xilinx_u280_xdma_201920_3/hash_anti_join.xclbin Loading: 'build_dir.hw.xilinx_u280_xdma_201920_3/hash_anti_join.xclbin' Kernel has been created DDR buffers have been mapped/copy-and-mapped Test Pass FPGA result 0: 28820357381.6672 Golden result 0: 28820357381.6672 FPGA execution time of 1 runs: 352393 usec Average execution per run: 352393 usec INFO: kernel 0: execution time 342568 usec ---------------------------------------------