- Build and run one of the following using U200 platform
cd L1/tests/jpegdec make run PLATFORM=xilinx_u200_gen3x16_xdma_2_202110_1.xpfm CSIM=1 # PLATFORM is case-insensitive and support awk regex. # Alternatively, the FPGA part can be speficied via XPART. When XPART is set, PLATFORM will be ignored. make run XPART=xcu200-fsgd2104-2-e CSIM=1 # delete generated files make clean
- Change input jpeg file for test
vi run_hls.tcl
# update the *.jpg path after the "-JPEGFile"
-JPEGFile *.jpg
Example csim output:
------------ Test for decode image.jpg ------------- WARNING: Vitis_Libraries/codec/L1/images/t0.jpg will be opened for binary read. 51193 entries read from Vitis_Libraries/codec/L1/images/t0.jpg hls_mcuv=33, hls_mcuh=39, hls_mcuc=1287, huffman 1 bits codes is :0b0000000000000000 huffman 2 bits codes is :0b0000000000000000 huffman 3 bits codes is :0b0000000000000010 huffman 4 bits codes is :0b0000000000001110 huffman 5 bits codes is :0b0000000000011110 huffman 6 bits codes is :0b0000000000111110 huffman 7 bits codes is :0b0000000001111110 huffman 8 bits codes is :0b0000000011111110 huffman 9 bits codes is :0b0000000111111110 huffman 10 bits codes is :0b0000001111111110 huffman 11 bits codes is :0b0000011111111100 huffman 12 bits codes is :0b0000111111111000 huffman 13 bits codes is :0b0001111111110000 huffman 14 bits codes is :0b0011111111100000 huffman 15 bits codes is :0b0111111111000000 huffman 16 bits codes is :0b1111111110000000 ... the end 3 blocks before zigzag are : ffffffb6, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ffffffe6, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0015, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, Ready for next image! INFO: [SIM 211-1] CSim done with 0 errors.
In order to facilitate user observation, the key module prints out the last three 8x8 DCT coefficients of the last MCU, including a Y, U and V.