Implemention - 2023.1 English

Vitis Libraries

Release Date
2023.1 English

The input JPEG and output Features:

Table 1 : jpegDecoder Features

Table 5 Table 1 jpegDecoder Features
jpegDecoder Status
Input support JPEG that scaned by baseline sequential processing 8-bit precision
Output YUV with the mcu scan order
Output info Image width, height, scan format, quantization tables, number of mcu, other details… the reason for the decoding error if there is
performance decode one Huffman symbol in 1 cycle Output YUV raw data 8 Byte per cycle with the mcu scan order

The algorithm implemention is shown as the figure below:

Figure 2 : jpegDecoder architecture on FPGA

Figure 2 jpegDecoder architecture on FPGA

As we can see from the figure:

The design uses the special statistical characteristics of jpeg compression, that is, in most cases, the (huffman length + value length) is less than 15, and each clock cycle can solve a huffman symbol.