Using GT Kernels and Ethernet IPs on Alveo - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

Version: Vitis 2023.1

The AMD Alveo™ Data Center accelerator cards provide networking connectivity such as one or two QSFP28 ports depending on the card. The QSFP28 interface can support a variety of Ethernet configurations including 10 GbE, 25 GbE, 40 GbE, and 100 GbE. Multiple instances of a single lane Ethernet protocol is also possible. With Vitis flow and the latest platforms, users can create register transfer level (RTL) kernels containing GTY transceivers, provide streaming connection to other kernels including high-level synthesis (HLS) compute units, datapath buffering into direct random access memory (DRAM) memories, and driver access for moving data between the host and FPGA by the Vitis tools to implement of full integrated design.

This simple tutorial illustrates the steps to include GTY transceivers in a RTL kernel and integrate it in top-level hardware overlay design with Vitis. The Alveo U200 card is used as example platform, and you could apply similar steps to other Alveo cards easily. Note the example design in this tutorial has no realistic functions and is just used for methodology explaination. Two lane number configurations (x1 and x4) are provided here.

To finish the example design steps in this tutorial, you will need at least two license keys: xxv_eth_mac_pcs and x_eth_mac. You can refer to 10G/25G Ethernet Subsystem Ordering Instructions for more information.