Use RTL Kernel Wizard to Create Kernel Frame - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

Now we use RTL Kernel Wizard to create the frame for rtc_gen kernel. We will launch the Wizard from Vivado. Please refer to Vitis Application Acceleration Development Flow Documentation for detailed user guide of RTL kernel and RTL Kernel Wizard.

Please change to ./rtc_gen directory of the git repo, create a directory named vivado_project, then enter this directory.

cd ./rtc_gen
mkdir vivado_project
cd ./vivado_project
vivado &

We create a new RTL project named rtc_gen_kernel in the just created vivado_project directory. During the part selection page, select *Alveo U200 Data Center Accelerator Card.


When the project is created, in the Flow Navigator, click the IP catalog command, type RTL Kernel in the IP catalog search box, then double-click RTL Kernel Wizard to launch the wizard.

In the General Settings tab of the RTL Kernel Wizard, set the kernel name to rtc_gen, set the kernel vendor to xilinx.com, change the has reset option to value 1, refer to below snapshot.


In the Scalars tab, configure the kernel arguments as our design specification. Refer to the Control Register table and below snapshot. Please note read_addr register is not considered scalar argument as AXI master pointer, so we don’t need to configure it in this tab. We are using uint as argument type here, though all these bit might not be used.


In the Global Memory tab, configure the AXI master interfaces parameters according to our design specification. Name the AXI master interface to fontread_axi_m, change the width to 4 bytes (32-bit), and set the relating argument name to read_addr. Refer to below snapshot.


In the Streaming interfaces tab, set the number of AXI4-Sttream interfaces to 1, name it to dataout_axis_m, set the mode the Master, and set the width to 8 bytes (64-bit). Refer to below snapshot.


Finally review the summary page of the wizard, and click OK button to generate the RTL kernel top level framework.


For the next “Generate Output Products” pop-up window, just click Skip button close the window. Now you can see the rtc_gen.xci file in the Design Sources group of Sources view. Right click the rtc_gen.xci file, select Open IP Example Design.


In the Open IP Example Design pop-up window directly click OK button, then another project named rtc_gen_ex will be created in ./vivado_project directory and open automatically in another Vivado session. We will use project rtc_gen_ex as the major working project to finish the rtc_gen kernel development.


In the rtc_gen_ex project, you can see a few automatically generated Verilog/SystemVerilog source code files:

rtc_gen_control_s_axi.v                 
rtc_gen_example_adder.v                
rtc_gen_example_axi_read_master.sv     
rtc_gen_example_axi_write_master.sv   
rtc_gen_example_counter.sv              
rtc_gen_example_number_generator.sv    
rtc_gen_example.sv 
rtc_gen_example_vadd_axis.sv
rtc_gen_example_vadd.sv
rtc_gen_tb.sv
rtc_gen.v

In the Sources view, Hierarchy tab, we can see the HDL file hierarchy. Now we have finished the kernel framework creation.