Tutorial Setup - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
Release Date
2023.1 English

Note: This tutorial showcases only hw_emu flow. If the user wants to run HW flow and has a server with multiple devices, they need to ensure that the correct device_index is used in the host code.

unsigned int device_index = 0;
std::cout << "Open the device" << device_index << std::endl;
auto device = xrt::device(device_index);
  1. To set up the Vitis core development kit, run the following commands.

      #setup Xilinx Vitis tools, XILINX_VITIS and XILINX_VIVADO will be set in this step. source <VITIS install path>/settings64.sh. for example:
      source /opt/Xilinx/Vitis/2023.1/settings64.sh
      #Setup runtime. XILINX_XRT will be set in this step
      source /opt/xilinx/xrt/setup.sh
  2. Execute the makefile to build the design for HW-Emulation.

    cd reference-files
    make all

    Makefile Options Descriptions

    • MODE := hw_emu: Set the build configuration mode to HW Emulation

    • PLATFORM := xilinx_u250_gen3x16_xdma_4_1_202210_1: Select the target platform

    • KERNEL_SRC := src/vadd.cpp: List the kernel source files

    • HOST_SRC := src/host.cpp: List the host source files

    As previously mentioned, the default implementation of the design uses a single DDR bank. Observe the messages in the Console view during the link step; you should see messages similar to the following.

    ip_name: vadd
    Creating apsys_0.xml
    INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to DDR[1]
    INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to DDR[1]
    INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.out to DDR[1]

    This confirms that the mapping is automatically inferred by the Vitis core development kit for each of the kernel arguments in the absence of explicit [connectivity] options being specified.

  3. Run HW-Emulation by executing the makefile with the run option.

    make run

    After the simulation is complete, the following memory connections for the kernel data transfer are reported.

    INFO: [Vitis-EM 22] [Wall clock time: 22:51, Emulation time: 0.0569014 ms] Data transfer between kernel(s) and global memory(s)
    vadd_1:m_axi_gmem0-DDR[1]          RD = 0.391 KB               WR = 0.000 KB
    vadd_1:m_axi_gmem1-DDR[1]          RD = 0.391 KB               WR = 0.000 KB
    vadd_1:m_axi_gmem2-DDR[1]          RD = 0.000 KB               WR = 0.391 KB

Now, you will explore how the data transfers can be split across the following:

  • DDR Bank 0

  • DDR Bank 1

  • DDR Bank 2