The Vivado Design Suite Project - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

At this point, the AMD Vivado™ Design Suite opens a project automatically with the generated RTL code corresponding to the default A = A + 1 function. You can navigate to review the source files or even run RTL simulation. However, for this tutorial, do not modify the default RTL Kernel and will only package into an object file (.xo).

  1. In Flow Navigator, click Generate RTL Kernel.
    Generate RTL Kernel

  2. In the Generate RTL Kernel dialog box, select the Sources-only packaging option.

  3. For Software Emulation Sources, you can add a C++ model of the RTL kernel, which is used for Software Emulation.

    The C++ model must be coded by the design engineer. Typically, there is no C++ model available, and Hardware Emulation is used to test the design. Because the RTL Wizard creates a C++ model of the vadd design, the steps to add this file are also provided below.

  4. Click the Browse command (...).

  5. Double-click the imports directory.

  6. Select the rtl_kernel_wizard_0_cmodel.cpp file and click OK.

  7. To generate the RTL kernel, click OK.

  8. After the RTL kernel has been generated successfully, click Yes to exit the Vivado Design Suite, and return to the Vitis IDE.

  9. A message window displays some information related to the generated RTL kernel. Review it and click OK.

  10. Exit the Vitis IDE.

At this point, you have packaged the RTL kernel into the following object file, rtl_kernel_wizard_0.xo found in the following directory.