Testbench - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

AMD provides a simple SystemVerilog testbench for the krnl_cbc module with AMD AXI VIPs. The testbench sources are in the ~/krnl_cbc/tbench directory. The krnl_aes module is instantiated in this testbench to connect with krnl_cbc via AXI-Stream link. Two AXI slave VIPs are used in memory mode, and two AXI master VIPs are used to configure the arguments and control the kernel execution.

For krnl_aes, the AXI master VIP emulates the ap_ctrl_hs protocol for AES key expansion operation. For krnl_cbc, the AXI master VIP emulates the ap_ctrl_chain protocol for consecutive task pushing. In the testbench, the input and output data are divided into groups including a number of words. Both input sync and output sync are emulated in the testbench. For more details, refer to the tb_krnl_cbc.sv file.

The input random data to the testbench is generated by a perl script ~/common/plain_gen.pl, and the reference data for output check is generated by OpenSSL tools. The shell script ~/krnl_cbc/runsim_krnl_cbc_xsim.sh is used to generate the input stimulus and output reference, and to run the simulation with Vivado XSIM.